(1) Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) gate array large scale integrated circuit (LSI) device, more particularly, to a gate array LSI in which various functions, such as an internal test circuit, can be realized by providing, on part of peripheral circuit regions on an LSI chip, a general-purpose cell array regions.
(2) Description of the Prior Art
CMOS gate array LSI's made by the master slice method have undergone continued development due to increasingly diverse LSI designer requirements and the strong need for easier LSI inspection.
A conventional CMOS gate array LSI comprises an internal cell array region for internal circuits, in which a plurality of CMOS basic cells including N channel MOS transistors and P channel MOS transistors having common gates, are arranged, and peripheral circuit regions, in which input buffer circuits, output buffer circuits, protective circuits, input/output pads, and so forth are arranged. The basic cells in the cell array region for the internal circuits can be appropriately wired for effective use as inverters, NAND gates, NOR gates, flip-flops, and so forth.
A problem arises, however, in that the transistors in the peripheral circuit regions are laid out in such a manner that only limited circuits, such as input buffer circuits, output buffer circuits, and bi-directional buffer circuits, can be realized. Other circuits, for example, Schmitt trigger circuits and clock gate circuits, cannot be formed in the peripheral circuit regions.
Shift registers also cannot be formed in the peripheral circuit regions. Since a test circuit requires shift registers, a circuit for testing circuits formed in the internal cell array region cannot be formed in the peripheral circuit regions. Formation of a test circuit in the internal cell array region itself would use up part of the internal cell array region and, thus, prevent effective utilization of the region.
Another problem is that the number of transistors forming the input buffer circuit on the peripheral circuit regions is smaller than the number of transistors forming the output buffer circuit or the bi-directional buffer circuit, i.e., the input/output buffer circuit. Also, the transistors in the peripheral circuit regions are regularly arranged with the same pattern. Therefore, there are excessive transistors in the region where the input buffer circuit is formed, that is, where a bi-directional buffer circuit is not formed. The extra transistors are not used for other applications and, thus, are useless. It should be noted that, regardless of the utilization of the peripheral circuit regions, the area of the regions cannot be reduced because a power supply line and ground line must be extended onto the regions.